View ADP130AUJZ-25-R7_3760470.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

350 ma, low v in , low quiescent current, cmos linear regulator adp130 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2008 C 2010 analog devices, inc. all rights reserved. features 350 ma maximum output current input voltage supply range v bias = 2.3 v to 5.5 v v in = 1.2 v t o 3.6 v 2.3 v < v in < 3.6 v, vin can be tied to vbias very low dropout voltage: 17 mv @ 1 0 0 ma load low quiescent current: 25 a @ no load low shu tdown current: <1 a 1% accuracy @ 25c excellent psrr performance: 7 0 db @ 10 khz excellent load/line transient response optimized for small 1 f ceramic capacitors current limit and thermal overload protection logic controlled enable 5- lead tsot package applications mobile phones digital camera and audio devices portable and battery - powered equipment post dc - to - dc regulation typical applicatio n circuit s 06963-001 adp130 1 vin 2 gnd 3 en 5 vout 4 vbias + v in = 1.8v v out = 1.2v 1f + 1f v bias = 3.6v + 1f off on figure 1. 06963-002 adp130 1 vin 2 gnd 3 en 5 vout 4 vbias + v in = 2.8v v out = 1.8v 1f + 1f v bias = 5v + 1f off on figure 2. general description the adp130 is a low quiescent current, low dropout linear regu - lator. it is designed to operate in dual - supply mode with an input voltage as low as 1.2 v to increase efficiency and provide up to 350 ma of output current. the low 17 mv dropout voltage at a 10 0 ma load improves efficie ncy and allows operation over a wider input voltage range. a dual - supply power solution typically improves conversion efficiency over a single - supply solution because the higher v b ias supply powers the part, and the lower v in supply delivers current to the load. the power dissipated in the device is thereby reduced. the adp130 is optimized for stable operation with small 1 f ceramic output capacitors. the adp130 delivers good transient performance with minimal board area. t he adp130 is available in fixed output voltage s ranging from : 0.80 v to 3 .0 v . the adp130 ha s a typ ical internal soft start time of 200 s. short - circ uit protection and thermal overload protection circuits prevent damage in adverse conditions. the adp130 is available in a tiny 5- lead tsot package for the smallest footprint solution to meet a variety of portable power applications .
adp130 rev. b | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuits ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 input and output capacitor: recommended specifications . 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ..............................................7 theory of operation ...................................................................... 12 applications information .............................................................. 13 capacitor selection .................................................................... 13 undervoltage lockout ............................................................... 14 enable feature ............................................................................ 14 current limit and thermal overload protection ................. 15 thermal consideration s ............................................................ 15 junction temperature calculations ......................................... 16 pcb layout considerations ...................................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 5/ 10 rev. a to rev. b changes figure 1 and figure 2 ....................................................... 1 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 18 3 /0 9 rev. 0 to rev. a changes to table 2 ............................................................................ 4 changes to figure 18 to figure 21 .................................................. 9 changes to figure 22 to 26 ............................................................ 10 7/08 revision 0: initial version
adp130 rev. b | page 3 of 20 specifications v in = v out + 0. 4 v, v bias = 5 v, i out = 1 0 ma, c in = 1 f, c out = 1 f, c bias = 1 f, t a = 25c, unless otherwise noted. table 1 . parameter symbol conditions min typ max unit input voltage range v in t j = ? 40c to +125c 1.2 3.6 v bias voltage range v bias t j = ? 40c to +125c 2.3 5.5 v operating supply current i vin 1 i out = 0 a 25 a i out = 0 a, t j = ? 40c to +125c 44 a i out = 1 ma 40 a i out = 1 m a, t j = ? 40c to +125c 58 a i ou t = 10 0 ma 10 0 a i out = 10 0 ma, t j = ? 40c to +125c 1 30 a i out = 350 ma 160 a i out = 350 ma, t j = ? 40c to +125c 22 0 a bias operating current i bias 16 a t j = ? 40c to +125c 28 a shutdown current i sd -vin en = gnd 0.1 a en = gnd, t j = ? 40c to + 8 5c 1. 0 a en = gnd, t j = +85c to +125c 20 a i sd - vbias en = gnd 0.1 a en = gnd, t j = ? 40c to +125c 1 .0 a fixed output voltage accuracy v out i out = 10 ma ?1 +1 % 1 m a < i out < 350 ma, v in = (v out + 0 .4 v) to 3.6 v ?2 +2 % 1 m a < i out < 350 ma, v in = (v out + 0. 4 v) to 3.6 v , t j = ? 40c to +125c ?3 +3 % line regulation ?v out / ?v in v in = (v out + 0.4 v) to 3.6 v, t j = C 40c to +125c ? 0.10 +0.1 0 %/ v load regulation 2 ?v out / ?i out i out = 1 0 ma to 350 ma 0.001 %/ ma i out = 1 0 ma to 350 ma, t j = ? 40c to +125c 0.005 %/ ma dropout voltage 3 v dropout i out = 1 0 ma, v bias = 2.3 v, v out = 3 v 2 mv i out = 1 0 ma, v bias = 2.3 v, v out = 3 v , t j = ? 40c to +125c 3 .5 mv i out = 1 00 ma, v bias = 2. 3 v, v out = 3 v 17 mv i out = 1 0 0 ma, v bias = 2.3 v, v out = 3 v , t j = ? 40c to +125c 28 mv i out = 350 ma, v bias = 2.3 v, v out = 3 v 70 mv i out = 350 ma, v bias = 2.3 v, v out = 3 v , t j = ? 40c to +125c 100 mv start - up time 4 t start - up v out = 1.2 v 200 s current limit threshold 5 i limit 400 55 0 1000 ma thermal shutdown thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd - hys 15 c en input en input logic high v ih 2.3 v v bias 5.5 v 1.2 v en input logic low v il 2.3 v v bias 5.5 v 0.4 v en input leakage current v i- leakage en = bias or gnd 0.1 a en = bias or gnd, t j = ? 40c to +125c 1 a undervoltage lockout uvlo input voltage rising uvlo rise t j = ?40c to +125c 2.1 v input voltage falling uvlo fal l t j = ?40c to +125c 1.5 v hysteresis uvlo hys 18 0 mv
adp130 rev. b | page 4 of 20 parameter symbol conditions min typ max unit output noise out noise 10 hz to 100 khz , v in = 3.6 v, v out = 0.8 v 29 v rms 10 hz to 100 khz , v in = 3.6 v, v out = 1.2 v 38 v rms 10 hz to 100 khz , v in = 3.6 v, v out = 1.5 v 43 v rms 10 hz to 100 khz , v in = 3.6 v, v out = 2.5 v 61 v rms 10 hz to 100 khz , v in = 3.6 v, v out = 3.0 v 77 v rms power supply rejection ratio psrr modulated bias, 10 khz, v out = 3.0 v , v in = 3.6 v, v bias = 5 v 70 db modulated bias, 100 khz, v out = 3.0 v , v in = 3.6 v, v bias = 5 v 53 db modulated v in , 10 khz, v out = 1.2 v , v in = v out + 1 v, v bias = 5 v 70 db modulated v in , 100 khz, v out = 1.2 v , v in = v out + 1 v, v bias = 5 v 54 db modulated v in , 10 khz, v out = 0.8 v , v in = v out + 1 v, v bias = 5 v 70 db modulated v in , 100 khz, v out = 0.8 v , v in = v out + 1 v, v bias = 5 v 55 db 1 i vin = i gnd ? i bias , where i gnd is the current flowing from the gnd pin. 2 based on an endpoint calculation using 1 ma and 35 0 ma loads. 3 dropout voltage is defined as the input - to - output voltage differential when the input voltage is set to the nominal output volta ge. this applies only for output voltages above 1.3 v. 4 start - up time is defined as the time from the rising edge of en to vout being at 90% of its nominal value. 5 current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for example, the current limit for a 2.0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 2.0 v, or 1.8 v. input and output cap acitor : recommended specific ations table 2 . parameter symbol condit ions min typ max unit minimum input and output c apacitance 1 c min t a = ? 40c to +125c 0.70 1 f capacitor esr r esr t a = ?40c to +125c 0 .001 1 ? 1 the minimum input and output capacitance should be >0.70 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r and x5r type capa citors are recommended. y5v and z5u cap acitors are not recommended for use with any ldo.
adp130 rev. b | page 5 of 20 absolute maximum rat ings table 3 . parameter rating v in to gnd ?0.3 v to + 3.6 v v bias to gnd ?0.3 v to +6 v en to gnd ?0.3 v to +6 v v out to gnd ?0.3 v to v in storage temperature range ? 65c to +150c operating temperature range ? 40c to +125c operating junction temperature 125c lead temperature (soldering, 10 sec) 300c stresses above those listed under absolute maximum ratings may cause p ermanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating c onditions for extended periods may affect device reliability. t hermal d ata absolute maximum ratings apply only individually , not in combi - nation. the adp130 may be damaged when junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that the junction temperature is within th e specified temperature limits. in applications with high power dissipation and poor thermal resistance , the maximum ambient tempe rature may need to be derated. in applications with moderate power di ssipation and low pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction tempera ture (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ) , and the junction - to - ambient thermal resistance of the package ( ja ). t j is calculate d using the following formula : t j = t a + ( p d ja ) the j unction - to - ambient thermal resistance ( ja ) of the package is bas ed on modeling and calculation using a four - layer board. the junction - to - ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board desig n is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the s pecified value s of ja are based on a four - layer, 4 in 3 in circuit board. for details about board construction, refer to jedec jesd51 - 7. jb is th e junction - to - board thermal characterization parameter with units of c / w. jb of the package is based on modeling and calculation using a four - layer board. the jedec jesd51 - 12 document, guide lines for reporting and using package thermal information , state s that thermal characterization parameters are not th e same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than a single path , as in thermal resistance ( jb ). therefore, jb thermal paths include conv ection from the top of the package as well as radiation from the package, factors that make jb more usef ul in real world applications. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ), using the fo llowing formula : t j = t b + ( p d jb ) r efer to the jedec jesd51 - 8 and jesd51 - 12 documents for more detailed information about jb . thermal resistance ja and jb are specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance package type ja jb unit 5- lead tsot 170 43 c/w esd caution
adp130 rev. b | page 6 of 20 pin configuration and function descripti ons adp130 top view (not to scale) 1 vin 2 gnd 3 en 5 vout 4 vbias 06963-003 figure 3 . pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 vin regulator input supply. bypass vin to gnd with a capacitor of 1 f or greater. 2 gnd ground. 3 en enable input. drive en high to turn on the regulator; drive en low to turn off the regulator. for automatic startup, connect en to vbias 4 v bias bias input s upply. connect a capacitor of 1 f or greater between vbias and gnd . 5 v out regulated output voltage. bypass vout to gnd with a capacitor of 1 f or greater.
adp130 rev. b | page 7 of 20 typica l performance charac teristics v bias = 5 v, v in = 2.2 v, v out = 1. 8 v, i out = 1 0 ma, c in = c out = c bias = 1 f, t a = 25c, unless otherwise noted. 06963-004 v out (v) junction temperature (c) ?40 ?5 25 85 125 i load = 10ma i load = 1ma 1.775 1.780 1.785 1.790 1.795 1.800 1.805 i load = 350ma i load = 100ma i load = 50ma i load = 200ma figure 4 . output voltage vs. junction temperature 06963-005 v out (v) i load (ma) 1 10 100 1000 1.795 1.797 1.799 1.801 1.803 1.805 figure 5 . output voltage vs. load current 06963-006 v in (v) v out (v) 1.795 1.796 1.797 1.798 1.799 1.800 1.801 1.802 1.803 1.804 1.805 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 200ma i load = 350ma figure 6 . output voltage vs. input voltage ?40 ?5 25 85 125 06963-007 junction temperature (c) i vin current (a) 0 200 20 40 60 80 100 120 140 160 180 i load = 100ma i load = 200ma i load = 350ma i load = 1ma i load = 10ma i load = 50ma figure 7. i vin current vs. junction temperature ?40 ?5 25 85 125 06963-008 junction temperature (c) bias current (a) 0 5 10 15 20 25 30 i load = 350ma i load = 200ma i load = 100ma i load = 50ma i load = 10ma i load = 1ma figure 8. bias current vs. junction te mperature 06963-009 i vin current (a) i load (ma) 1 10 100 1000 0 20 40 60 80 100 120 140 160 180 figure 9. i vin current vs. load current
adp130 rev. b | page 8 of 20 06963-010 bias current (a) i load (ma) 1 10 100 1000 0 5 10 15 20 25 figure 10 . bias current vs. load current 0 20 40 60 80 100 120 140 160 180 200 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 i load = 350ma i load = 200ma 06963-011 v in (v) ground current (a) i load = 1ma i load = 10ma i load = 50ma i load = 100ma figure 11 . ground current vs. input voltage 0 5 10 15 20 25 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 06963-012 v in (v) bias current (a) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 200ma i load = 350ma figure 12 . bias current vs. input voltage 06963-013 i load (ma) dropout voltage (mv) 0 10 20 30 40 50 60 10 100 1000 v out = 3v t a = 25 c figure 13 . dropout voltage vs. load current , v out = 3 v 06963-014 i load (ma) dropout voltage (mv) 10 100 1000 0 10 20 30 40 50 60 70 80 t a = 25 c v out = 3.0v v out = 1.8v figure 14 . dropout voltage vs. output voltage and load current 06963-015 v in (v) v out (v) 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 i load = 10ma i load = 50ma i load = 100ma i load = 200ma i load = 350ma figure 15 . ou tput voltage vs. input voltage (in dropout) , v out = 3 v
adp130 rev. b | page 9 of 20 06963-016 v in (v) ground current (a) 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 0 100 200 300 400 500 600 i load = 10ma i load = 50ma i load = 100ma i load = 200ma i load = 350ma figure 16 . gro und current vs. input voltage (in dropout) , v out = 3 v 06963-017 v in (v) bias current (a) 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 13 14 15 16 17 18 i load = 100ma i load = 50ma i load = 10ma i load = 350ma i load = 200ma figure 17 . b ias current vs. input voltage (i n dropout ), v out = 3 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m v ripple = 50mv v in = 3.6v v out = 3.0v c out = 1f v bias = 5v 06963-018 frequency (hz) psrr (db) load = 100a load = 10ma load = 100ma load = 350ma fi gure 18 . power supply rejection ratio vs. frequency, v in input ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m v ripple = 50mv v in = 2.8v v out = 1.8v c out = 1f v bias = 5v 06963-019 frequency (hz) psrr (db) load = 100a load = 10ma load = 100ma load = 350ma figure 19 . power supply rejection ratio vs. frequency, v in input ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m v ripple = 50mv v in = 2.2v v out = 1.2v c out = 1f v bias = 5v 06963-020 frequency (hz) psrr (db) load = 100ma load = 350ma load = 100a load = 10ma figure 20 . power supply rejection ratio vs. frequency, v in input ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k 1m 10m v ripple = 50mv v in = 1.8v v out = 0.8v c out = 1f v bias = 5v 06963-021 frequency (hz) psrr (db) load = 100a load = 10ma load = 100ma load = 350ma figure 21 . power supply rejection ratio vs. frequency, v in input
adp130 rev. b | page 10 of 20 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m 06963-022 frequency (hz) psrr (db) 1v headroom 0.5v headroom v ripple = 50mv v out = 1.8v i out = 100ma c out = 1f v bias = 5v figure 22 . power supply rejection ratio vs. headroom, v in input 10 100 1k 10k 100k 1m 10m v ripple = 50mv v in = 3.6v v out = 3.0v c out = 1f v bias = 2.3v 06963-023 frequency (hz) psrr (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 load = 350ma load = 100ma load = 10ma load = 100a figure 23 . power supply rejection ratio vs. frequency, v bias input ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m v ripple = 50mv v in = 2.8v v out = 1.8v c out = 1f v bias = 2.3v 06963-024 frequency (hz) psrr (db) load = 350ma load = 100ma load = 10ma load = 100a figure 24 . power supply rejection ratio vs. frequency, v bias input ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m v ripple = 50mv v in = 2.2v v out = 1.2v c out = 1f v bias = 2.3v 06963-025 frequency (hz) psrr (db) load = 350ma load = 100ma load = 10ma load = 100a figure 25 . power supply rejection ratio vs. frequency, v bias input 10 100 1k 10k 100k 1m 10m v ripple = 50mv v in = 1.8v v out = 0.8v c out = 1f v bias = 2.3v 06963-026 frequency (hz) psrr (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 load = 350ma load = 100ma load = 10ma load = 100a figure 26 . power supply rejection ratio vs. frequency, v bias input 0.01 0.1 1 10 10 100 1k 10k 100k 06963-027 frequency (hz) noise (v/ hz) 0.8v 1.5v 3.0v figure 27 . noise spec trum vs . v out
adp130 rev. b | page 11 of 20 0 10 20 30 40 50 60 70 80 90 0.01 0.1 1 10 100 1000 06963-028 i load (ma) noise (v rms) 0.8v 1.2v 1.5v 1.8v 2.5v 3.0v figure 28 . output noise vs. load current and output voltage 06963-029 ch1 200m a ch2 50mv m40s a ch1 92m a 2 1 t 10.40% 1ma to 350ma load step 2.5a/s 200ma/div i load v out 50mv/div figure 29 . load transient response 06963-030 ch1 500mv ch2 2mv m40s a ch1 3.35v 2 1 1 t 10.20% 3v to 3.5v input voltage step 2v/s 500mv/div v bias v in = 3.6v v out 2mv/div figure 30 . v bias line transient response, v in = 3.6 v, i out = 350 ma 06963-031 ch1 500mv ch2 5mv m20s a ch1 3.37v 2 1 t 10.20% 3v to 3.5v input voltage step 2v/s v in v out 5mv/div figure 31 . v in line transient response, v bias = 5 v, i out = 1 ma 06963-032 ch1 500mv ch2 5mv m20s a ch1 3.27v 2 1 t 10.20% 3v to 3.5v input voltage step 2v/s v in v out 5mv/div figure 32 . v in li ne transient response, v bias = 5 v, i out = 350 ma
adp130 rev. b | page 12 of 20 theory of operation the adp130 is a low dropout , linear regulator that use s an advanced proprietary architecture t o achieve low quiescent current and high efficiency regulation. it also provides high powe r supply rejection ratio (psrr) and excellent line and load transient response using a small 1 f ceramic output capacitor. the device operate s from a 2.3 v to 5.5 v bias rail and a 1.2 v to 3.6 v input rail to provide up to 350 m a of output current. supply current in shutdown mode is typically less than 1 a. internally, the adp130 consists of a reference, an error ampli - fier, a feedback voltage divider, and a pass device. the output current is delivered via the pass device, which is controlled by the error amplifier, forming a negative feedback system that ideally drives the feedback voltage to equal the reference voltage. if the feedback voltage is lower than the reference voltage, the negative feedback drives more current, incre asing the output voltage. if the feedback voltage is higher than the reference voltage, the negative feedback drives less current, decreasing the output voltage. t he vbias pin is the po sitive supply for all circuitry except the pass device . the adp130 ha s an internal soft start that limits the output voltage ramp period to approximately 200 s. all internal devices are controlled by the enable pin, en. when en is high , the output is on; when en is low, the output is off . shutdown vin gnd en vout vbias r1 r2 06963-033 short-circuit, uvlo, and thermal protect 0.5v ref figure 33 . internal block diagram the adp130 is available in output voltage s ranging from 0.8 v to 3.0 v. the adp130 use s the en pin to enable and disable the v out pin under normal operating conditions. when en is high, v out turns on. when en is low, v out turns o ff. for auto - matic startup, en can be tied to v bias .
adp130 rev. b | page 13 of 20 applications information capacitor selection output capacitor the adp130 is designed for operation with small, space -saving ceramic capacitors, but it functions with most commonly used capacitors as lo ng as care is taken regarding the effective series resistance (esr) value. the esr of the output capacitor affects the stability of the ldo control loop. a minimum of 0.70 f capaci tance with an esr of 1 ? or less is recommended to ensure stability of the adp130 . transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the adp130 to large changes in load current. figure 34 an d figure 35 show the transient responses for output capacitance values of 1 f and 10 f, respectively. 06963-034 ch1 200m a ch2 50mv m400ns a ch1 192ma 2 1 t 14% v out = 1.8v c in = c out = 1f 1ma to 350ma load step 2.5a/s 200ma/div i load v out 50mv/div figure 34 . output transient response, c out = 1 f 06963-035 ch1 200m a ch2 50mv m400ns a ch1 160ma 2 1 t 13% v out = 1.8v c in = c out = 10f 1ma to 350ma load step 2.5a/s 200ma/div i load v out 50mv/div figure 35 . output tr ansient response, c out = 10 f input bypass capacitor connecting a 1 f capacitor from v in to gnd reduces the circuit sensitivity to pcb layout, especially when long input traces or high source impedance are encountered. if > 1 f of output capacitance is required, the input capacitor should be increased to match it. bias capacitor connecting a 1 f capacitor from v bias to gnd reduces the circuit sensitivity to pcb layout, especially when long input traces or high source impedance are encountered. input, bias, and output capacitor properties any good quality ceramic capacitor can be used with the adp130 , as long as it meet s the minimum capacitance and maximum esr requirements. ceramic cap acitors are manufactured with a variety of dielectrics, each with dif ferent behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v ar e recommended. y5v and z5u dielectrics are not recommended for use with any ldo , due to their poor temperature and dc bias characteristics. figure 36 show s the capacitance vs . voltage bias characteristic s of the 0402 1 f, 1 0 v, x 5r capacitor. the voltage stability of a capaci tor is strongly influenced by the capa citor size and voltage rating. in general, a capacitor in a larger package or higher voltage rating exhibit s better stability. the temperature variation of the x5r dielect ric is about 15% over the ? 40 to + 85 c temperature range and is not a function of the package or voltage rating. 0 0.2 0.4 0.6 0.8 1.0 1.2 0 2 4 6 8 10 06963-036 voltage (v) capacitance (f) figure 36 . capacitance vs . voltage characteristic s
adp130 rev. b | page 14 of 20 use eq uation 1 to determine the worst - case capacitance , account ing for capacitor variation over temperature, compo - nent tolerance, and voltage. c eff = c out (1 ? tempco ) (1 ? tol ) (1) where: c eff is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol i s the worst - case component tolerance . in this example, tempco over ?40c to +85c is assumed to be 15% for an x5r dielectric. tol is assumed to be 10%, and c out = 0.94 f at 1.8 v , as shown in figure 36. substituting these values in equation 1 yields the following : c eff = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0.719 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over tempera - ture and tolerance at the chosen output voltage. to gua rantee the performance of the adp130 , it is imperative that the effects of dc bias, temperature , and tolerances on the behavior of the capacitors be evaluated for each application. undervoltage lockout the adp130 ha s an internal undervoltage lockout circuit that disables all inputs and the output when the input voltag e is less than approximately 2 .1 v. this ensures that the adp130 inputs and the output behave in a predictable manner during power - up. enable feature the adp130 uses the en pin to enable and di sable the v out pin under normal operating conditions. as shown in figure 37, when a rising voltage on en crosses the active threshold, v out turns on. when a falling voltage on en crosses the inactive threshold, v out turns off. 06963-037 ch1 500mv ch2 500mv m10ms a ch2 640mv 1 t 30% 2 v out = 1.8v c in = c out = 1f v out 500mv/div en 500mv/div figure 37 . typical en pin operation as shown in figure 37 , the en pin has built - in hysteresis. this prevents on/off oscillations that can occur due to noise on the en pin as it passes through the thresho ld points. the en pin active and inactive thresholds are derived from the v in voltage. therefore, these thresholds vary with changing input voltage. figure 38 shows typical en active and inactive thresholds when the v bias voltage varies from 2.3 v to 5.5 v . 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 06963-038 v bias (v) threshold (v) en active en inactive figure 38 . typical en pin thresholds vs. input the adp130 u ses an internal soft start to limit the inrush curre nt when the output is enabled. the start - up time for the 0 .8 v option is approximately 18 0 s from the time at which the en active threshold is crossed to when the output reaches 90% of its final valu e. the start - up time depends somewhat on the output voltage setting and increases slightly as the output voltage increases. 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 100 200 300 400 500 600 700 800 900 1000 06963-039 time (s) voltage (v) v bias = 2.3v v in = 3.6v i load = 10ma enable 3.0v 1.8v 1.2v 0.8v figure 39 . typical start - up t ime for various output voltages
adp130 rev. b | page 15 of 20 current limit and thermal ov erload protection the adp130 is protected against damage due to excessive power dissipation by current limit and thermal overload protection circuits. the adp1 30 is designed to current limit when the output load reaches 5 5 0 ma (typical). w hen the output load exceeds 55 0 ma, the output voltage is reduced to maintain a constant current limit. thermal overload protection limits the junction temperature to a maximum of 150c typical. under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 150c, the output is turned off, reducing output current to zero. when the junction temperature drops below 135c, the output is turned on again and output current is restored to its nominal value. consider the case where a hard short from v out to gnd occurs. at first , the adp130 current limit s so that only 55 0 ma is co n- ducted into the short. if self - heati ng of the junction is great enough to cause its temperature to rise above 150c, thermal shutdown activates, turning off the output and reducing the output current to zero. as the junction temperature cools and drops below 135c, the output turns on and co nducts 55 0 ma into the short, again causing the junction temperature to rise above 150c. this thermal oscillation between 135c and 150c causes a current oscillation between 5 5 0 ma and 0 ma that continues as long as the short remains at the output. curre nt limit and thermal overload protections protect the device against accidental overload conditions. for reliable operation, device power dissipation must be externally limited so that junction temperatures do not exceed 125c. thermal consideratio ns to g u arantee reliable operation, the junction temperature of the adp130 must not exceed 125c. to ensure that the junction tem - pera ture stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. these parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air ( ja ). the value of ja is dependent on the package assembly compounds used and the amount of copper to which the gnd pins of the package are soldered on the pcb. table 6 shows typical ja values of t he 5 - lead tsot package for various pcb copper sizes. table 6 . typical ja values for specified pcb copper sizes copper size (mm 2 ) ja ( c/w) 0 1 170 50 152 100 146 300 134 500 131 1 device soldered to minimum size pin traces. the junction temperature of the adp130 can be calculated from the following equation: t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) (3) where: v in and v out are the input and output voltages, respectively. i load is the load current. i gnd is the ground current. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation can be simplified as fo llows: t j = t a + {[( v in ? v out ) i load ] ja } (4) as shown in equation 4 , for a given ambient temperature, input - to - output voltage differential, and continuous load current, a minimum copper size requirement exists for the pcb to ensure that the junction temperature does not rise above 125c. figure 40 through figure 46 show junction temperature calculations for different ambient temperatures, load currents, v in to v out differentials, and areas of pcb copper.
adp130 rev. b | page 16 of 20 junction temp erature calculations 140 0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1ma 10ma 50ma 100ma 150ma 250ma 350ma (i load ) max t j (do not operate above this point) 06963-040 0.4 0.8 1.2 1.6 2.0 2.4 2.8 figure 40 . 500 mm 2 of pcb copper, t a = 25c, tsot 140 0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1ma 10ma 50ma 100ma 150ma 250ma 350ma max t j (do not operate above this point) 06963-041 0.4 0.8 1.2 1.6 2.0 2.4 2.8 (i load ) figure 41 . 100 mm 2 of pcb copper, t a = 25c, tsot 140 0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1ma 10ma 50ma 100ma 150ma 250ma 350ma max t j (do not operate above this point) 06963-042 0.4 0.8 1.2 1.6 2.0 2.4 2.8 (i load ) figure 42 . 0 mm 2 of pcb copper, t a = 25c, tsot 140 0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1ma 10ma 50ma 100ma 150ma 250ma 350ma max t j (do not operate above this point) 06963-043 0.4 0.8 1.2 1.6 2.0 2.4 2.8 (i load ) figure 43 . 500 mm 2 of pcb copper, t a = 50c, tsot 140 0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1ma 10ma 50ma 100ma 150ma 250ma 350ma max t j (do not operate above this point) 06963-044 0.4 0.8 1.2 1.6 2.0 2.4 2.8 (i load ) figure 44 . 100 mm 2 of pcb copper, t a = 50c , ts ot 140 0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1ma 10ma 50ma 100ma 150ma 250ma 350ma max t j (do not operate above this point) 06963-045 0.4 0.8 1.2 1.6 2.0 2.4 2.8 (i load ) figure 45 . 0 mm 2 of pcb copper, t a = 50c , tsot
adp130 rev. b | page 17 of 20 in cases where bo ard temperature is known, use the thermal char - acterization parameter, jb , to estimate the junction tem perature rise. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ), using the following formula: t j = t b + ( p d jb ) (5) the typical value of jb is 42.8c/w for the 5 - lead tsot package. 140 0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1ma 10ma 50ma 100ma 150ma 250ma 350ma max t j (do not operate above this point) 06963-046 0.4 0.8 1.2 1.6 2.0 2.4 2.8 (i load ) figure 46 . tsot, t a = 85c p cb layout consideration s heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the adp130 . however, as shown in table 6 , a point of diminishing return is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. the input capacitor should be placed as close as possible to the v in and gnd pins. the output capacitor should be placed as close as possible to the v out and gnd pins. using 0402 or 0603 size capacitors and resistors achieves the smallest possible foot - print solution on boards where the area is limited. 06963-047 vbias j1 analog devices adp130-xx-evalz vin vout gnd en gnd c1 c2 gnd gnd u1 c3 figure 47 . example tsot pcb layout
adp130 rev. b | page 18 of 20 outline dimensions 100708-a * compliant to jedec standards mo-193-ab with the exception of package height and thickness. 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.20 0.08 0.60 0.45 0.30 8 4 0 0.50 0.30 0.10 max * 1.00 max * 0.90 max 0.70 min 2.90 bsc 5 4 1 2 3 sea ting plane figure 48 . 5 - lead thin small outline transistor package [tsot] (uj- 5) dimensions show in millimeters ordering guide model 1 temperature range output volta ge (v) 2 package description package option branding adp130aujz -0.8- r7 ? 40c to +125c 0.8 5- lead tsot uj -5 lch adp130aujz -1.2- r7 ? 40c to +125c 1.2 5- lead tsot uj -5 lcj adp130aujz -1.5- r7 ? 40c to +125c 1.5 5- lead tsot uj -5 lck adp130aujz -1.8- r7 ? 40c to +125c 1.8 5- lead tsot uj -5 lcl adp130aujz -2.5- r7 ? 40c to +125c 2.5 5- lead tsot uj -5 lcm adp130 -0.8- evalz ? 40c to +125c 0.8 evaluation board adp130 -1.2- evalz ? 40c to +125c 1.2 evaluation board adp130 -1.5- evalz ? 40c to +125c 1.5 evaluati on board adp130 -1.8- evalz ? 40c to +125c 1.8 evaluation board adp130 -2.5- evalz ? 40c to +125c 2.5 evaluation board adp130 ujz - redykit evaluation board kit adp130 - bl1 - evz blank evaluation board 1 z = rohs compliant part. 2 for additional voltage options, contact your local analog devices, inc., sales or distribution representative.
adp130 rev. b | page 19 of 20 notes
adp130 rev. b | page 20 of 20 notes ? 2008 C 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06963 -0- 5/10(b)

▲Up To Search▲

Price & Availability of ADP130AUJZ-25-R7

	To Download ADP130AUJZ-25-R7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .